1. Field of the Invention
The present invention relates to an inverter and a chopper type comparator using the same, and, more particularly, to a technique of making the layout of a power source of an analog circuit in a semiconductor integrated circuit and setting a circuit constant.
2. Description of the Related Art
A description will be given below of a chopper type comparator for typical use in conventional A/D comparators. FIG. 3 exemplifies the use of a chopper type comparator. In this diagram, reference numeral 1 denotes the main part of a chopper type comparator, reference numeral 2 a sample and hold circuit of the comparator, Q.sub.1 and Q.sub.2 N and P channel field effect transistors (IG-FET) which constitute an inverter 3, Q.sub.3 and Q.sub.4 feedback switching transistors, V.sub.DD and V.sub.SS power sources, C a capacitor, SW1 and SW2 switches whose switching operations are controlled by signals .phi. and .phi., V.sub.ref a reference voltage, and A.sub.in a comparator input.
Referring to FIG. 3, the switch SW1 on the A.sub.in side and the feedback switches Q.sub.3, Q.sub.4 of the inverter 3 are turned ON to accumulate charges in the capacitor C. Since the inverter 3 has its input and output short-circuited at this time, the potential at the point A equals a threshold value V.sub.C of the inverter 3. The charges Q accumulated in the capacitor C can therefore be given by: EQU Q=(V.sub.C -A.sub.in) C (1)
Then, the switches SW1, Q.sub.3 and Q.sub.4 are turned OFF and the switch SW2 on the V.sub.ref side is turned ON. As the amount of charges accumulated in the capacitor C does not vary, with V.sub.A being the potential of the point A, the following can be derived: EQU Q=(V.sub.A -V.sub.ref) C (2)
From equations (1) and (2), we can attain: EQU V.sub.A =V.sub.C +(V.sub.ref -A.sub.in) (3)
FIG. 4 illustrates the input-output characteristic of a typical inverter. The point where the linear line V.sub.in =V.sub.out intersects the characteristic curve is the threshold value V.sub.C of the inverter. From this diagram, it is understood that when an input voltage is off V.sub.C, even slightly, this deviation will appear in amplified manner in the output. That is, EQU V.sub.1 '-V.sub.C =.alpha..sub.1 (V.sub.C -V.sub.1) EQU V.sub.C -V.sub.2 '=.alpha..sub.2 (V.sub.2 -V.sub.C)
where .alpha..sub.1 and .alpha..sub.2 are amplification factors of the inverter 3.
From the equation (3), therefore, if A.sub.in is smaller than V.sub.ref, the output V.sub.A1 (= V.sub.out) of the comparator would be: ##EQU2## and if A.sub.in is greater than V.sub.ref, the output V.sub.A2 (= V.sub.out) of the comparator would be: ##EQU3##
The conventional comparators should be concerned with an offset initiated by the resistors in the power sources because of the following reason. As the input of the inverter 3 is at the middle level at the sampling time (at which charges are being accumulated in the capacitor C with SW1, Q.sub.3 and Q.sub.4 all being ON), the P and N type transistors Q.sub.2 and Q.sub.1 of the inverter are both turned ON to thereby permit a through current to flow between the power sources V.sub.DD and V.sub.SS. Given that I.sub.p is the through current at that time and R.sub.S and R.sub.D are a source resistor of the inverter on the side of the reference power source (V.sub.SS) and a source resistor on the side of the supplying power source (V.sub.DD), respectively, the potential on the V.sub.SS side increases by I.sub.p R.sub.S while the potential on the V.sub.DD side falls by I.sub.p R.sub.D. The threshold value V.sub.C at this time can be given by: ##EQU4## where V.sub.TN and V.sub.TP are the threshold voltages of N and P type transistors, respectively, L.sub.N and W.sub.N are the channel length and width of the N type transistor, L.sub.p and W.sub.p are the channel length and width of the P type transistor, .mu..sub.N and .mu..sub.p are the mobilities of electrons and holes, and E.sub.OX and t.sub.OX are the dielectric constant and thickness of a gate oxide film.
When the operation enters a comparing period (unlike in the sampling time, only SW2 being turned ON), the input potential of the inverter varies from V.sub.C, thus causing the through current to become to I.sub.p '. The threshold value V.sub.C ' at this time is ##EQU5## From the equations (5) and (6) it should be understood that V.sub.C and V.sub.C ' have the following relationship: ##EQU6## Therefore, the actual charges Q' accumulated in the capacitor C at the sampling time is EQU Q'=(V.sub.C +.DELTA.V-A.sub.in) C.
From this equation, the potential V.sub.A at the point A at the time a comparison is made will be EQU V.sub.A =V.sub.C +(V.sub.ref -A.sub.in)+.DELTA.V (7)
Comparing the equation (3) with the equation (7) shows that an offset of .DELTA.V occurs according to the prior art.
To reduce the offset originated from the resistors of power sources, efforts have been made to make the resistances of these resistors as small as possible. This has resulted in thick power wires, which causes larger chip size. Minimizing the resistances also restricts the location of the comparator.